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Old 11-15-06, 11:20 PM   #130 (permalink)
mbloof
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Join Date: Jan 2006
Location: Oregon
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Designers route ALL pins to testpoints when using ICT (in circuit test) so they can BOUNDRY SCAN the BGA device, IE: make sure all pins are soldered.

Common on many PCB's, even those with active parts on both sides, surely not enough room on the Axim 50/51 PCB.

The USB host would require only two pins wired to the Intel chip: D+ and D- as power and ground would be picked up elsewhere.

Power would need to be fused, filtered and switched via a FET or small "allinone" chip that had all these functioned intergrated (saving PCB space).

The data lines would need to be routed as a MATCHED PAIR and terminated with a matching network and ESD protection (also sometimes done with a small "all in one device".

If the two needed signals were routed to the connector, the matching network and ESD protection would need to placed and routed, but not need to be populated.
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