|
Originally Posted by mbloof
|
Designers route ALL pins to testpoints when using ICT (in circuit test) so they can BOUNDRY SCAN the BGA device, IE: make sure all pins are soldered.
Common on many PCB's, even those with active parts on both sides, surely not enough room on the Axim 50/51 PCB.
The USB host would require only two pins wired to the Intel chip: D+ and D- as power and ground would be picked up elsewhere.
Power would need to be fused, filtered and switched via a FET or small "allinone" chip that had all these functioned intergrated (saving PCB space).
The data lines would need to be routed as a MATCHED PAIR and terminated with a matching network and ESD protection (also sometimes done with a small "all in one device".
If the two needed signals were routed to the connector, the matching network and ESD protection would need to placed and routed, but not need to be populated.
|
Sorry, but not ALL the pins are brought out these days. there are other methods used to perform boundary scans. Correct circuit operation can be interpreted via other means and there is not enough board realestate around nowadays for a pile of testpoints that will only be used once - so I'm waiting to get a board so I can find out IF the signals are available.
I'm still curious about the test points along the edge of the board. As for the ESD protection chip, that can be grabbed from any junked USB device or just use a few zeners for spike and reverse protection.